The Field Programmable Gated Array (FPGA), digital system designs are prototyped and meant to be performance analyzed and verified on a general platform. Unlike FPGA, analog systems design cannot be tested for unless the design is fabricated on an integrated circuit (IC) and then subjected to testing. Therefore a flexible platform comparable to FPGA is necessary for verification of analog system designs. Application range of Field Programmable Analog Array (FPAA) besides limited, are not very versatile in the market. These FPAA’s do not expedite the easier debugging and reconfigurability for analog designs under test. Therefore, in this thesis work, we try to simulate an array of memory elements built using Floating Gate Transistors and implemented a novel algorithm that would aid in programming the charge storage capability of these transistors, which is based on (FPAA). The previously mentioned algorithm uses Fowler-Nordheim tunneling for global erase and hot-electron injection for programming large arrays of analog computational memory elements.
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