In most of the digital signal processing applications the main operation is multiplication and the speed of the digital signal processors is mainly determined by the speed of the multipliers used in the processor. The execution time of most digital signal processors algorithms depends on it multipliers and hence need for high speed multiplier arises , so to reduce the delay and speed up the digital signal processors a new multipliers are designed using Vedic mathematics techniques. Vedic mathematics is mainly based on 16 sutras (or aphorisms) and was re discovered in twentieth century. The proposed multiplier technique is from” urdhva tiryakbhayam sutra “which is one of the sutras in Vedic mathematics. Now we are going to code this technique in VHDL and synthesis using Quartus II. So we can calculate delay, speed , execution time of the proposed multiplier and can see the performance of multiplier by comparing to some standard multipliers used in the processors.
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