In the VLSI design, weighing options between speed, area and power are the major constraints. Hence, to achieve optimum result among these three parameters is very important. The generation of carry signals in an adder is the most time consuming process. The design of the efficient adder circuit is of high importance. There are different energy recovery schemes which are already proposed. This paper presented a comparative performance analysis of the adiabatic schemes such as 2N2N-2P and PFAL. The energy recovery characteristics of the above schemes are compared with the conventional CMOS adder. In this paper, we analyzed the power dissipation among the conventional CMOS adder, PFAL and 2N2N2-2P adiabatic circuits, and we proved that PFAL is better for inverter based circuits. For one bit full adder circuits 2N2N-2P performed better at low frequencies whereas at very high frequencies (200MHZ upward) PFAL performed better. Here we used Lt-spice for simulation results, and the size of the transistors are chosen based on 180nm technology.
March 24, 2015
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