A typical architecture of the LMS algorithm suffers from large on-chip area as numerous adders, multipliers and delay registers are employed in its design. Due to the recursion, pipelining is not possible with LMS algorithm. Delayed LMS (DLMS) is an improvised form of LMS algorithm which allows pipelining of different tasks. An effective architecture of a novel partial product generator followed by an efficient adder is adopted here to implement a delayed LMS adaptive filter. This architecture helped in scaling down adaptation delay and on-chip area, which are the major drawbacks of conventional prototype. An error-computation block followed by a weight-update block is employed to obtain better performance. This new architecture was implemented in a hardware description language and all the design constraints of the digital filter were studied on different FPGA‟s.
June 30, 2015
The right to download or print any of the pages of this thesis (Material) is granted by the copyright owner only for personal or classroom use. The author retains all proprietary rights, including copyright ownership. Any reproduction or editing or other use of this Material by any means requires the express written permission of the copyright owner. Except as provided above, or any use beyond what is allowed by fair use (Title 17 Section 107 U.S.C.), you may not reproduce, republish, post, transmit or distribute any Material from this web site in any physical or digital form without the permission of the copyright owner of the Material. Inquiries regarding any further use of these materials should be addressed to Administration, Jernigan Library, Texas A&M University-Kingsville, 700 University Blvd. Kingsville, Texas 78363-8202, (361)593-3416.