Designing a chip to obtain maximum performance and maintaining decent voltage levels with low power dissipations in a power distribution network (PDN) is a perplexing work. In this thesis, a firm model is used by fitting together with a power distribution network including on-chip decoupling capacitor of a typical system-on-chip for the analysis and approximating the value of the least value on-chip decoupling capacitance. Employing a firm model, design region is anticipated for the PDN with the help of AC, DC and transient noise derivations. Design region benefits the person who designs the circuit to enhance the power distribution network for chips that require more power such as SoC, for specified system parameters like inductance, frequency and power source voltage. The NETLIST is created for the complete power system of the firm model including the system-on-chip and simulated using the HSPICE for confirming the accuracy of the firm model. Results of the simulation include the steady state and transient voltage loss of the power distribution network. Also, influence of the system parameters on the design region is observed. It is observed that, design region reduces as there is an expansion in the network. Using this approach, designer enhances the power distribution system with the help of design region by trading off the design parameters such as decoupling capacitance.
July 20, 2015
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